The performance benefits of prefetching data and/or instructions from a system memory into a cache memory of a microprocessor are well-known, and as the disparity between memory access latency and the microprocessor core clock frequency continue to increase, those benefits become more important. However, the generation of prefetch requests by the microprocessor places additional load upon the limited resources of the microprocessor that are also needed by normal load and store requests, such as the external bus of the microprocessor, the bus interface unit that interfaces the microprocessor to the bus, and the various cache memories of the microprocessor. Thus, it is important to design the prefetcher in a way that efficiently utilizes those resources.